{
  "version": "1.0",
  "kicad_tools_version": "0.20.0",
  "generated_at": "2026-09-10T07:05:15.642258+00:00",
  "manufacturer": "jlcpcb",
  "files": {
    "README.txt": {
      "sha256": "4b7b0e9660e2aa83bd4e231f363834f43770763ace68d34c8a291b4f93aabc77",
      "size": 1628
    },
    "assembly-back.pdf": {
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      "size": 6889
    },
    "assembly-front.pdf": {
      "sha256": "9f8cc9aeb8cde9d3e9939ebdc72ab46ec37fa4659f145d77914847a1560c955d",
      "size": 10990
    },
    "bom_jlcpcb.csv": {
      "sha256": "9f279e0b3cbe583b95b3b7af202a91f6825e67e4451e7ae3b438b7d42d12efdd",
      "size": 240
    },
    "check-report.json": {
      "sha256": "7b3086bdc045808a7fe577cb303cd456b814d36383dc5ec6d1b8a490be758592",
      "size": 2615
    },
    "cpl_jlcpcb.csv": {
      "sha256": "fa86f220fefc8d3d7b135c6f78e9133f55d22bd5a6042f1548f79eae2afadc30",
      "size": 181
    },
    "gerbers/gerbers.zip": {
      "sha256": "2278ddf4643643af76322d4b595962ef77b6985b1116cdb1d2702ce2d9214400",
      "size": 10777
    },
    "images/assembly.png": {
      "sha256": "aa15c2fb2edfd5c74c4036fb9a48ec061a6e150033108b19ccf858be29dcbb38",
      "size": 92425
    },
    "images/layer_B_Cu.png": {
      "sha256": "4b7a385f1f96e0f3e3930865a7f7ae9edc42c94c2aeb41d1e46c602d4dc03ad0",
      "size": 72775
    },
    "images/layer_F_Cu.png": {
      "sha256": "7990055ce11278c62634aa0d16f34b1c63ca73b7863e15fb78fa523c38da2982",
      "size": 95339
    },
    "images/pcb_back.png": {
      "sha256": "2840f06f93b5a9e6f1e97d101a4fdc7b692746f2b0a539e89a010762e9b6b42f",
      "size": 74883
    },
    "images/pcb_copper.png": {
      "sha256": "1a814e38960c470499b263c66545fd30a4eb03aca14f1a935f20679ce9a6b211",
      "size": 78037
    },
    "images/pcb_front.png": {
      "sha256": "8f857bf4390d6081dbfe1f6ed22567b647ee76ac62f19fe8c3c496258a325efd",
      "size": 114289
    },
    "images/schematic_voltage_divider.png": {
      "sha256": "db430fe52f933af9198927fd1c0b4e91088495b3bff0370fba527ff930249638",
      "size": 118128
    },
    "kicad_project.zip": {
      "sha256": "dd7be1d6eb2a0d84cccd67df317d4e298459c209d7092d552b7048b1d8e6bd73",
      "size": 14088
    },
    "native-drc.json": {
      "sha256": "74de5a146838ba9fab6a0cc9de717dc9aa825d3f9c2fd4b18f1baac10602c0e4",
      "size": 1214
    },
    "procurement-review.md": {
      "sha256": "25eec92b01f7b00c1cc9cb4e0c9370f30d51efba672ad249a72b7968de5924cf",
      "size": 10341
    },
    "report.md": {
      "sha256": "c899bae9ca417164133f5efb256d9dcc5833fc066fae4c1a9d40a6f156895dc6",
      "size": 2799
    },
    "report.pdf": {
      "sha256": "d59062f84226bf46f7b42d669eea8dcfa3cb3ae4ec6d1f0f766494b690af8318",
      "size": 742702
    },
    "schematic.pdf": {
      "sha256": "4d97753027c11bae9d1d75545fab9e189c67b38fc3152239f98f8e14b9f61abd",
      "size": 47873
    }
  },
  "board": {
    "name": "voltage_divider_routed",
    "pcb_file": "voltage_divider_routed.kicad_pcb"
  },
  "preflight": [
    {
      "name": "pcb_file",
      "status": "OK",
      "message": "PCB file parsed successfully",
      "details": "Footprints: 4"
    },
    {
      "name": "schematic_file",
      "status": "OK",
      "message": "Schematic auto-detected: voltage_divider.kicad_sch"
    },
    {
      "name": "schematic_footprints",
      "status": "OK",
      "message": "All schematic symbols have a footprint assigned"
    },
    {
      "name": "board_outline",
      "status": "OK",
      "message": "Board outline is closed (5 points)"
    },
    {
      "name": "footprints",
      "status": "OK",
      "message": "All 4 footprints have library footprint names"
    },
    {
      "name": "board_dimensions",
      "status": "OK",
      "message": "Board dimensions within limits (30.00 x 25.00 mm)"
    },
    {
      "name": "drill_holes",
      "status": "OK",
      "message": "Drill holes present (2 vias, 4 TH pads)"
    },
    {
      "name": "tht_in_cpl",
      "status": "OK",
      "message": "2 through-hole component(s) excluded from CPL",
      "details": "THT references: J1, J2"
    },
    {
      "name": "bom_fields",
      "status": "OK",
      "message": "All 4 BOM items have required fields",
      "details": "4 active item(s) will receive LCSC from spec overlay"
    },
    {
      "name": "bom_lcsc_values",
      "status": "OK",
      "message": "No LCSC value/package mismatches detected (0 assigned item(s) checked against local parts cache)"
    },
    {
      "name": "bom_pcb_match",
      "status": "OK",
      "message": "BOM and PCB references match (4 components)"
    },
    {
      "name": "bom_cpl_match",
      "status": "OK",
      "message": "BOM and CPL references match (2 components, 2 THT excluded)"
    },
    {
      "name": "drc",
      "status": "WARN",
      "message": "No DRC report found; run kicad-cli or kct check first",
      "details": "Use --drc-report to specify a report file, or --skip-drc to skip"
    },
    {
      "name": "erc",
      "status": "WARN",
      "message": "No ERC report found; run kicad-cli first",
      "details": "Use --erc-report to specify a report file, or --skip-erc to skip"
    }
  ],
  "mode": "assembly",
  "warning_counts": {},
  "native_warning_counts": {},
  "acknowledged_warning_rules": [],
  "documentation_refresh": {
    "updated_at": "2026-09-10T21:50:06.229926+00:00",
    "issue": 5048,
    "scope": "Procurement documentation and package integrity only; original fabrication checks unchanged."
  }
}