{
  "version": "1.0",
  "kicad_tools_version": "0.20.0",
  "generated_at": "2026-09-10T19:21:49.220035+00:00",
  "manufacturer": "jlcpcb",
  "files": {
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    "firmware/charlieplex.hex": {
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      "size": 623
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    "firmware/main.c": {
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    "gerbers/gerbers.zip": {
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    "images/assembly.png": {
      "sha256": "40fee37f26278a7010579b755959f1667ce65f5b80ff17cd4e95ef60a35fd519",
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    "images/layer_B_Cu.png": {
      "sha256": "24062715d92c8e03c691b64ca89b5109903182e32af49cd29f570bbabb412bd1",
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    "images/layer_F_Cu.png": {
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    "images/pcb_back.png": {
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    "images/pcb_copper.png": {
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    "images/schematic_charlieplex_3x3.png": {
      "sha256": "3aecbe589a9c36091f9eb0b6dd452ae3bc7f23930352eac3bc9c94abff52e4f2",
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    "kct-check.json": {
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    "kicad_project.zip": {
      "sha256": "e4ca798cec3f14575e321e86cd7160957662219ea472067c9fb64369fd2fc4b1",
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    "lvs.json": {
      "sha256": "356b61ec235c657fe133747d662656d6f96f88531c6e0e77250dee36c9dab123",
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    },
    "native-drc.json": {
      "sha256": "10b4130104028acee503fb33c1ded8826543f6da10573be3811c41df99dc8385",
      "size": 1214
    },
    "native-erc.json": {
      "sha256": "86f037fd6dd7c342b545bcff6602eff25c8e5f6879777d12284472037def736d",
      "size": 988
    },
    "project.kct": {
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    "renders/3d-back.png": {
      "sha256": "693b35456fff9101078ef1e1a2200acaf361246307eaca132f513be0ba0f264a",
      "size": 200705
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    "renders/3d-front.png": {
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    "renders/pcb-back.svg": {
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      "size": 86532
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    "report.md": {
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      "size": 3421
    },
    "report.pdf": {
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      "size": 1707642
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    "schematic.pdf": {
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      "size": 85904
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  },
  "board": {
    "name": "charlieplex_3x3_routed",
    "pcb_file": "charlieplex_3x3_routed.kicad_pcb"
  },
  "preflight": [
    {
      "name": "pcb_file",
      "status": "OK",
      "message": "PCB file parsed successfully",
      "details": "Footprints: 19"
    },
    {
      "name": "schematic_file",
      "status": "OK",
      "message": "Schematic file found: charlieplex_3x3.kicad_sch"
    },
    {
      "name": "schematic_footprints",
      "status": "OK",
      "message": "All schematic symbols have a footprint assigned"
    },
    {
      "name": "board_outline",
      "status": "OK",
      "message": "Board outline is closed (5 points)"
    },
    {
      "name": "footprints",
      "status": "OK",
      "message": "All 19 footprints have library footprint names"
    },
    {
      "name": "board_dimensions",
      "status": "OK",
      "message": "Board dimensions within limits (50.00 x 55.00 mm)"
    },
    {
      "name": "drill_holes",
      "status": "OK",
      "message": "Drill holes present (28 vias, 16 TH pads)"
    },
    {
      "name": "tht_in_cpl",
      "status": "OK",
      "message": "3 through-hole component(s) excluded from CPL",
      "details": "THT references: J1, J2, U1"
    },
    {
      "name": "bom_fields",
      "status": "OK",
      "message": "All 19 BOM items have required fields",
      "details": "19 active item(s) will receive LCSC from spec overlay"
    },
    {
      "name": "bom_lcsc_values",
      "status": "OK",
      "message": "No LCSC value/package mismatches detected (0 assigned item(s) checked against local parts cache)"
    },
    {
      "name": "bom_pcb_match",
      "status": "OK",
      "message": "BOM and PCB references match (19 components)"
    },
    {
      "name": "bom_cpl_match",
      "status": "OK",
      "message": "BOM and CPL references match (16 components, 3 THT excluded)"
    },
    {
      "name": "drc",
      "status": "OK",
      "message": "DRC: 0 errors, 0 warnings"
    },
    {
      "name": "erc",
      "status": "OK",
      "message": "ERC: 0 errors, 0 warnings"
    }
  ],
  "mode": "assembly"
}