{
  "version": "1.0",
  "kicad_tools_version": "0.20.0",
  "generated_at": "2026-09-10T07:42:54.537851+00:00",
  "manufacturer": "jlcpcb-tier1",
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    "images/assembly.png": {
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    "images/layer_B_Cu.png": {
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    "images/layer_F_Cu.png": {
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    "images/pcb_copper.png": {
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    "images/schematic_stm32_devboard.png": {
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  },
  "board": {
    "name": "stm32_devboard_routed",
    "pcb_file": "stm32_devboard_routed.kicad_pcb"
  },
  "preflight": [
    {
      "name": "pcb_file",
      "status": "OK",
      "message": "PCB file parsed successfully",
      "details": "Footprints: 17"
    },
    {
      "name": "schematic_file",
      "status": "OK",
      "message": "Schematic auto-detected: stm32_devboard.kicad_sch"
    },
    {
      "name": "schematic_footprints",
      "status": "OK",
      "message": "All schematic symbols have a footprint assigned"
    },
    {
      "name": "board_outline",
      "status": "OK",
      "message": "Board outline is closed (5 points)"
    },
    {
      "name": "footprints",
      "status": "OK",
      "message": "All 17 footprints have library footprint names"
    },
    {
      "name": "board_dimensions",
      "status": "OK",
      "message": "Board dimensions within limits (60.00 x 40.00 mm)"
    },
    {
      "name": "drill_holes",
      "status": "OK",
      "message": "Drill holes present (29 vias, 8 TH pads)"
    },
    {
      "name": "tht_in_cpl",
      "status": "OK",
      "message": "2 through-hole component(s) excluded from CPL",
      "details": "THT references: J1, Y1"
    },
    {
      "name": "bom_fields",
      "status": "OK",
      "message": "All 17 BOM items have required fields",
      "details": "16 active item(s) will receive LCSC from spec overlay"
    },
    {
      "name": "bom_lcsc_values",
      "status": "OK",
      "message": "No LCSC value/package mismatches detected (1 assigned item(s) checked against local parts cache)"
    },
    {
      "name": "bom_pcb_match",
      "status": "OK",
      "message": "BOM and PCB references match (17 components)"
    },
    {
      "name": "bom_cpl_match",
      "status": "OK",
      "message": "BOM and CPL references match (15 components, 2 THT excluded)"
    },
    {
      "name": "drc",
      "status": "OK",
      "message": "DRC: 0 errors, 0 warnings"
    },
    {
      "name": "erc",
      "status": "OK",
      "message": "Native ERC: 0 errors, 0 warnings; native-erc.json",
      "details": "Verified after source correction"
    }
  ],
  "mode": "assembly",
  "manual_assembly": [
    "J1 SWD header",
    "Y1 HC49 crystal"
  ],
  "manufacturing_requirements": {
    "layers": 2,
    "via_type": "through",
    "minimum_via_drill_mm": 0.15,
    "minimum_via_diameter_mm": 0.3,
    "minimum_via_annular_ring_mm": 0.075,
    "via_covering": "Tented",
    "paid_factory_option": "0.15 mm minimum via hole size",
    "via_in_pad": false,
    "source": "https://jlcpcb.com/capabilities/pcb-capabilities/"
  },
  "warning_counts": {},
  "native_warning_counts": {}
}