Voltage Divider Test

Current evidence passes the assembly release checks; this does not establish tested hardware performance.

• zone fill: passed — Saved copper area agrees with an independent refill on 2 layer(s).
• Connectivity and design checks: passed — 0 electrical/manufacturing errors; DRC and ERC sub-checks passed; warning counts: none. Manifest verification is deferred to the artifacts gate.
• Native design rules (DRC): passed — 0 error-level findings on saved copper.
• native refilled drc: passed — 0 error-level findings on saved copper.
• lvs: passed — LVS PASSED over 8 bound pad(s).
• warning review: passed — Per-rule warning table reviewed: none.
• Manufacturing artifacts: passed — Fresh assembly bundle of 20 file(s); SHA256 integrity and source ZIP provenance verified.
• Bill of materials: passed — 3 BOM line(s) carry procurement identifiers; part check OK: 4 of 4 assigned item(s) verified against offline catalog and parts cache; no LCSC value/package mismatches; CPL includes 2 through-hole component(s) for fab assembly.

Passed: this check passed for the recorded files. Failed: this check found a problem. Not run: no result was established. Unlisted checks have no reported result.